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e preliminary jul y 1998 order number: 290606-006 n high-density symmetrically-blocked architecture ? 64 128-kbyte erase blocks (64 m) ? 32 128-kbyte erase blocks (32 m) n 4.5 v C5.5 v v cc operation ? 2.7 v?3.6 v and 4.5 v?5.5 v i/o capable n configurable x8 or x16 i/o n 100 ns read access time (32 m) 150 ns read access time (64 m) n enhanced data protection features ? absolute protection with v pen = gnd ? flexible block locking ? block erase/program lockout during power transitions n industry-standard packaging ? bga* package (64 m), ssop and tsop packages (32 m) n cross-compatible command support ? intel basic command set ? common flash interface ? scaleable command set n 32-byte write buffer ? 6.3 s per byte effective programming time n 6,400,000 total erase cycles (64 m) 3,200,000 total erase cycles (32 m) ? 100,000 erase cycles per block n automation suspend options ? block erase suspend to read ? block erase suspend to program n system performance enhancements ? sts status output n expanded temperature operation C20 c to +70 c n intel ? strataflash? memory flash technology capitalizing on two-bit-per-cell technology, intel? strataflash? memory products provide 2x the bits in 1x the space. offered in 64-mbit (8-mbyte) and 32-mbit (4-mbyte) densities, intel strataflash memory devices are the first to bring reliable, two-bit-per-cell storage technology to the flash market. intel strataflash memory benefits include: more density in less space, lowest cost-per-bit nor devices, support for code and data storage, and easy migration to future devices. using the same nor-based etox? technology as intels one-bit-per-cell products, intel strataflash memory devices take advantage of 400 million units of manufacturing experience since 1988. as a result, intel strataflash components are ideal for code or data applications where high density and low cost are required. examples include networking, telecommunications, audio recording, and digital imaging. by applying flashfile? memory family pinouts, intel strataflash memory components allow easy design migrations from existing 28f016sa/sv, 28f032sa, and word-wide flashfile memory devices (28f160s5 and 28f320s5). intel strataflash memory components deliver a new generation of forward-compatible software support. by using the common flash interface (cfi) and the scaleable command set (scs), customers can take advantage of density upgrades and optimized write capabilities of future intel strataflash memory devices. manufactured on intels 0.4 micron etox? v process technology, intel strataflash memory provides the highest levels of quality and reliability. intel? strataflash? memory technology 32 and 64 mbit 28f320j5 and 28f640j5
2 information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 28f320j5 and 28f640j4 may contain design defects or errors known as errata. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 5937 denver, co 8021-9808 or call 1-800-548-4725 or visit intels website at http://www.intel.com copyright ? intel corporation 1997, 1998 cg-041493 *third-party brands and names are the property of their respective owners.
e intel ? strataflash? memory technology, 32 and 64 mbit 3 preliminary contents page page 1.0 product overview ...................................5 2.0 principles of operation .....................11 2.1 data protection ..........................................12 3.0 bus operation .........................................12 3.1 read ..........................................................13 3.2 output disable ...........................................13 3.3 standby......................................................13 3.4 reset/power-down ....................................13 3.5 read query................................................14 3.6 read identifier codes.................................14 3.7 write ..........................................................14 4.0 command definitions ............................14 4.1 read array command................................18 4.2 read query mode command.....................18 4.2.1 query structure output .......................18 4.2.2 query structure overview ...................20 4.2.3 block status register ..........................21 4.2.4 cfi query identification string.............22 4.2.5 system interface information...............23 4.2.6 device geometry definition .................24 4.2.7 primary-vendor specific extended query table .......................................25 4.3 read identifier codes command ...............26 4.4 read status register command................27 4.5 clear status register command................27 4.6 block erase command ..............................27 4.7 block erase suspend command................27 4.8 write to buffer command ...........................28 4.9 byte/word program commands.................28 4.10 configuration command...........................29 4.11 set block and master lock-bit commands................................................29 4.12 clear block lock-bits command ..............30 5.0 design considerations ........................40 5.1 three-line output control..........................40 5.2 sts and block erase, program, and lock- bit configuration polling ............................40 5.3 power supply decoupling ..........................40 5.4 v cc , v pen , rp# transitions........................40 5.5 power-up/down protection ........................41 5.6 power dissipation.......................................41 6.0 electrical specifications..................42 6.1 absolute maximum ratings........................42 6.2 operating conditions..................................42 6.3 capacitance ...............................................42 6.4 dc characteristics .....................................43 6.5 ac characteristics read-only operations.................................................46 6.6 ac characteristics write operations.......48 6.7 block erase, program, and lock-bit configuration performance........................51 7.0 ordering information..........................52 8.0 additional information .......................53
intel ? strataflash? memory technology, 32 and 64 mbit e 4 preliminary revision history date of revision version description 09/01/97 -001 original version 09/17/97 -002 modifications made to cover sheet 12/01/97 -003 v cc /gnd pins converted to no connects specification change added i ccs , i ccd , i ccw , and i cce specification change added order codes specification change added 1/31/98 -004 the m bga* chip-scale package in figure 2 was changed to a 52-ball package and appropriate documentation added. the 64-mb m bga package dimensions were changed in figure 2. changed figure 4 to read ssop instead of tsop. 3/23/98 -005 32-mbit intel strataflash memory read access time added. the number of block erase cycles was changed. the write buffer program time was changed. the operating temperature was changed. a read parameter was added. several program, erase, and lock-bit specifications were changed. minor documentation changes were made as well. datasheet designation changed from advance information to preliminary. 7/13/98 -006 intel strataflash memory 32-mb m bga package removed. t ehel read specification reduced. table 4 was modified. the ordering information was updated.
e intel ? strataflash? memory technology, 32 and 64 mbit 5 preliminary 1.0 product overview the intel ? strataflash? memory family contains high-density memories organized as 8 mbytes or 4 mwords (64-mbit) and 4 mbytes or 2 mwords (32-mbit). these devices can be accessed as 8- or 16-bit words. the 64-mbit device is organized as sixty-four 128-kbyte (131,072 bytes) erase blocks while the 32-mbits device contains thirty-two 128- kbyte erase blocks. blocks are selectively and individually lockable and unlockable in- system. see the memory map in figure 5. a common flash interface (cfi) permits software algorithms to be used for entire families of devices. this allows device-independent, jedec id-independent, and forward- and backward- compatible software support for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. scaleable command set (scs) allows a single, simple software driver in all host systems to work with all scs-compliant flash memory devices, independent of system-level packaging (e.g., memory card, simm, or direct-to-board place- ment). additionally, scs provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. a command user interface (cui) serves as the interface between the system processor and internal operation of the device. a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. a block erase operation erases one of the devices 128-kbyte blo cks typically within one second independent of other blo cks. each block can be independently erased 100,000 times. block erase suspend mode allows system software to sus pend block erase to read or program data from any other block. each device incorporates a write buffer of 32 bytes (16 words) to allow optimum programming performance. by using the write buffer, data is programmed in buffer increments. this feature can improve system program performance by up to 20 times over non write buffer writes. individual block locking uses a combination of bits, block lock-bits and a master lock-bit, to lock and unlock blocks. block lock-bits gate block erase and program operations while the master lock-bit gates block lock-bit modification. three lock-bit configuration operations set and clear lock-bits (set block lock-bit, set master lock-bit, and clear block lock-bits commands). the status register indicates when the wsms block erase, program, or lock-bit configuration operation is finished. the sts (status) output gives an additional indicator of wsm activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). status indication using sts minimizes both cpu overhead and system power consumption. when configured in level mode (default mode), it acts as a ry/by# pin. when low, sts indicates that the wsm is performing a block erase, program, or lock-bit configuration. sts-high indicates that the wsm is ready for a new command, block erase is suspended (and programming is inactive), or the device is in reset/power-down mode. additionally, the configuration command allows the sts pin to be configured to pulse on completion of programming and/or block erases. three ce pins are used to enable and disable the device. a unique ce logic design (see table 2, chip enable truth table ) reduces decoder logic typically required for multi-chip designs. external logic is not required when designing a single chip, a dual chip, or a 4-chip miniature card or simm module. the byte# pin allows either x8 or x16 read/writes to the device. byte# at logic low selects 8-bit mode; address a 0 selects between the low byte and high byte. byte# at logic high enables 16-bit operation; address a 1 becomes the lowest order address and address a 0 is not used (dont care). a device block diagram is shown in figure 1. when the device is disabled (see table 2, chip enable truth table ) and the rp# pin is at v cc , the standby mode is enabled. when the rp# pin is at gnd, a further power-down mode is enabled which minimizes power consumption and provides write protection during reset. a reset time (t phqv ) is required from rp# switching high until outputs
intel ? strataflash? memory technology, 32 and 64 mbit e 6 preliminary are valid. likewise, the device has a wake time (t phwl ) from rp#-high until writes to the cui are recognized. with rp# at gnd, the wsm is reset and the status register is cleared. the intel strataflash memory devices are available in several package types. the 64-mbit is available in 56-lead ssop (shrink small outline package) and bga* package (micro ball grid array). the 32-mbit is available in 56-lead tsop (thin small outline package) and 56-lead ssop. figures 2, 3, and 4 show the pinouts. 32-mbit: thirty-two 64-mbit: sixty-four 128-kbyte blocks input buffer output multiplexer y-gating program/erase voltage switch data comparator status register identifier register data register i/o logic address latch address counter x-decoder y-decoder input buffer output buffer gnd v cc v pen ce 0 ce 1 ce 2 we# oe# rp# byte# command user interface 32-mbit: a 0 - a 21 64-mbit: a 0 - a 22 dq 0 - dq 15 v cc write buffer write state machine multiplexer query sts v ccq ce logic 0606_01 figure 1. intel ? strataflash? memory block diagram
e intel ? strataflash? memory technology, 32 and 64 mbit 7 preliminary table 1. lead descriptions symbol type name and function a 0 input byte-select address: selects between high and low byte when the device is in x8 mode. this address is latched during a x8 program cycle. not used in x16 mode (i.e., the a 0 input buffer is turned off when byte# is high). a 1 Ca 22 input address inputs: inputs for addresses during read and program operations. addresses are internally latched during a program cycle. 32-mbit: a 0 Ca 21 64-mbit: a 0 Ca 22 dq 0 Cdq 7 input/ output low-byte data bus: inputs data during buffer writes and programming, and inputs commands during command user interface (cui) writes. outputs array, query, identifier, or status data in the appropriate read mode. floated when the chip is de-selected or the outputs are disabled. outputs dq 6 Cdq 0 are also floated when the write state machine (wsm) is busy. check sr.7 (status register bit 7) to determine wsm status. dq 8 Cdq 15 input/ output high-byte data bus: inputs data during x16 buffer writes and programming operations. outputs array, query, or identifier data in the appropriate read mode; not used for status register reads. floated when the chip is de-selected, the outputs are disabled, or the wsm is busy. ce 0 , ce 1 , ce 2 input chip enables: activates the devices control logic, input buffers, decoders, and sense amplifiers. when the device is de-selected (see table 2, chip enable truth table ), power reduces to standby levels. all timing specifications are the same for these three signals. device selection occurs with the first edge of ce 0 , ce 1 , or ce 2 that enables the device. device deselection occurs with the first edge of ce 0 , ce 1 , or ce 2 that disables the device (see table 2, chip enable truth table ). rp# input reset/ power-down: resets internal automation and puts the device in power-down mode. rp#-high enables normal operation. exit from reset sets the device to read array mode. when driven low, rp# inhibits write operations which provides data protection during power transitions. rp# at v hh enables master lock-bit setting and block lock-bits configuration when the master lock-bit is set. rp# = v hh overrides block lock-bits thereby enabling block erase and programming operations to locked memory blocks. do not permanently connect rp# to v hh . oe# input output enable: activates the devices outputs through the data buffers during a read cycle. oe# is active low. we# input write enable: controls writes to the command user interface, the write buffer, and array blocks. we# is active low. addresses and data are latched on the rising edge of the we# pulse. sts open drain output status: indicates the status of the internal state machine. when configured in level mode (default mode), it acts as a ry/by# pin. when configured in one of its pulse modes, it can pulse to indicate program and/or erase completion. for alternate configurations of the status pin, see the configurations command. tie sts to v ccq with a pull-up resistor.
intel ? strataflash? memory technology, 32 and 64 mbit e 8 preliminary table 1. lead descriptions (continued) symbol type name and function byte# input byte enable: byte# low places the device in x8 mode. all data is then input or output on dq 0 Cdq 7 , while dq 8 Cdq 15 float. address a 0 selects between the high and low byte. byte# high places the device in x16 mode, and turns off the a 0 input buffer. address a 1 then becomes the lowest order address. v pen input erase / program / block lock enable: for erasing array blocks, programming data, or configuring lock-bits. with v pen v penlk , memory contents cannot be altered. v cc supply device power supply: with v cc v lko , all write attempts to the flash memory are inhibited. v ccq output buffer supply output buffer power supply: this voltage controls the devices output voltages. to obtain output voltages compatible with system data bus voltages, connect v ccq to the system supply voltage. gnd supply ground: do not float any ground pins. nc no connect: lead is not internally connected; it may be driven or floated.
e intel ? strataflash? memory technology, 32 and 64 mbit 9 preliminary gnd a 10 v pen ce 0 a 14 v cc a 7 a 9 a 11 a 12 a 15 a 17 a 4 a 19 a 6 a 8 rp# a 13 a 16 a 21 a 5 a 20 a 1 a 3 a 18 ce 1 a 2 a 22 byte# dq 7 ce 2 we# dq 8 dq 1 dq 6 dq 15 a 0 oe# dq 3 dq 12 dq 9 dq 2 dq 13 dq 14 dq 0 sts dq 11 dq 4 v cc (1) dq 10 dq 5 gnd (1) gnd v ccq gnd a 10 v pen ce 0 a 14 v cc a 7 a 9 a 11 a 12 a 15 a 17 a 4 a 19 a 6 a 8 rp# a 13 a 16 a 21 a 5 a 20 a 1 a 3 a 18 ce 1 a 2 a 22 byte# dq 7 ce 2 we# dq 8 dq 1 dq 6 dq 15 a 0 oe# dq 3 dq 12 dq 9 dq 2 dq 13 dq 14 dq 0 sts dq 11 dq 4 v cc (1) dq 10 dq 5 gnd (1) gnd v ccq a b c d e f g h i a b c d e f g h i 7 8 6543 21 2 1 3456 78 top view bottom view - ball side up nc (1) nc (1) nc (1) nc (1) 64-mbit intel ? strataflash? memory: 7.67 mm x 16.37 mm note: 1. v cc (ball i7), gnd (ball i2), and nc (balls f2 and f7) have been removed. future generations of intel strataflash memory may make use of these missing ball locations. figures are not drawn to scale. figure 2 . bga* package (64 mbit)
intel ? strataflash? memory technology, 32 and 64 mbit e 10 preliminary 28f320j5 intel ? strataflash? memory 56-lead tsop standard pinout 14 mm x 20 mm top view 1 3 4 2 5 7 8 6 9 11 12 10 13 15 16 14 17 19 20 18 21 23 24 22 25 27 28 26 56 54 53 55 52 50 49 51 48 46 45 47 44 42 41 43 40 38 37 39 36 34 33 35 32 30 29 31 nc a 21 a 20 ce 1 a 19 a 17 a 16 a 18 v cc a 14 a 13 a 15 a 12 v pen rp# ce 0 a 11 a 9 a 8 a 10 gnd a 6 a 5 a 7 a 4 a 2 a 1 a 3 28f016sv 28f016sa 28f032sa 3/5# nc a 20 ce 1 a 19 a 17 a 16 a 18 v cc a 14 a 13 a 15 a 12 v pp rp# ce 0 a 11 a 9 a 8 a 10 gnd a 6 a 5 a 7 a 4 a 2 a 1 a 3 3/5# ce 2 a 20 ce 1 a 19 a 17 a 16 a 18 v cc a 14 a 13 a 15 a 12 v pp rp# ce 0 a 11 a 9 a 8 a 10 highlights pinout changes a 6 a 5 a 7 a 4 a 2 a 1 a 3 gnd 28f160s5 nc nc a 20 ce 1 a 19 a 17 a 16 a 18 v cc a 14 a 13 a 15 a 12 v pp rp# ce 0 a 11 a 9 a 8 a 10 a 6 a 5 a 7 a 4 a 2 a 1 a 3 gnd nc oe# sts we# dq 15 dq 14 dq 6 dq 7 gnd dq 5 dq 12 dq 13 dq 4 gnd dq 11 v ccq dq 3 dq 2 v cc dq 10 dq 9 dq 8 dq 0 dq 1 a 0 nc ce 2 byte# 28f016sv 28f016sa 28f032sa wp# oe# ry/by# we# dq 15 dq 14 dq 6 dq 7 gnd dq 5 dq 12 dq 13 gnd dq 11 dq 3 dq 2 v cc dq 10 dq 9 dq 8 dq 0 dq 1 a 0 nc nc byte# wp# oe# ry/by# we# dq 15 dq 14 dq 6 dq 7 gnd dq 5 dq 12 dq 13 dq 11 dq 3 dq 2 v cc dq 10 dq 9 dq 8 dq 0 dq 1 a 0 nc nc byte# 28f320j5 28f160s5 wp# oe# sts we# dq 15 dq 14 dq 6 dq 7 gnd dq 5 dq 12 dq 13 gnd dq 11 dq 3 dq 2 v cc dq 10 dq 9 dq 8 dq 0 dq 1 a 0 nc nc byte# v cc dq 4 gnd v cc v cc dq 4 dq 4 0606_03 note: 1. v cc (pin 37) and gnd (pin 48) are not internally connected. for future device revisions, it is recommended that these pins be connected to their respected power supplies (i.e., pin 37 = v cc and pin 48 = gnd). 2. for compatibility with future generations of intel ? strataflash? memory, this nc (pin 56) should be connected to gnd. figure 3. tsop lead configuration (32 mbit)
e intel ? strataflash? memory technology, 32 and 64 mbit 11 preliminary intel ? strataflash? memory 56-lead ssop standard pinout 16 mm x 23.7 mm top view 1 3 4 2 5 7 8 6 9 11 12 10 13 15 16 14 17 19 20 18 21 23 24 22 25 27 28 26 56 54 53 55 52 50 49 51 48 46 45 47 44 42 41 43 40 38 37 39 36 34 33 35 32 30 29 31 v pen a 11 a 10 rp# a 9 a 2 a 3 a 1 a 4 a 6 a 7 a 5 gnd v cc dq 9 a 8 dq 1 dq 0 a 0 dq 8 byte# ce 2 dq 2 nc dq 10 dq 11 gnd dq 3 v pen a 11 a 10 rp# a 9 a 2 a 3 a 1 a 4 a 6 a 7 a 5 gnd v cc dq 9 a 8 dq 1 dq 0 a 0 dq 8 byte# ce 2 dq 2 nc dq 10 dq 11 gnd dq 3 v pp a 11 a 10 rp# a 9 a 2 a 3 a 1 a 4 a 6 a 7 a 5 gnd v cc dq 9 a 8 dq 1 dq 0 a 0 dq 8 byte# nc dq 2 nc dq 10 dq 11 gnd dq 3 28f640j5 28f320j5 28f320s5 28f640j5 28f320j5 highlights pinout changes. 28f320s5 ry/by# 28f160s5 28f016sv 28f016sa ce 0 a 13 a 14 a 12 a 15 ce 1 a 21 nc a 20 a 18 a 17 a 19 a 16 dq 6 v cc dq 14 dq 15 sts dq 7 oe# nc dq 13 we# dq 5 dq 4 v ccq dq 12 gnd ce 0 a 13 a 14 a 12 a 15 ce 1 a 21 a 20 a 18 a 17 a 19 a 16 dq 6 v cc dq 14 dq 15 sts dq 7 oe# nc dq 13 we# dq 5 dq 4 v ccq dq 12 a 22 gnd ce 0 # a 13 a 14 a 12 a 15 ce 1 # nc a 20 a 18 a 17 a 19 a 16 gnd dq 6 v cc dq 14 dq 15 ry/by# dq 7 oe# wp# dq 13 we# dq 5 dq 4 v cc dq 12 a 21 ce 0 # a 13 a 14 a 12 a 15 ce 1 # nc a 20 a 18 a 17 a 19 a 16 gnd dq 6 v cc dq 14 dq 15 dq 7 oe# wp# dq 13 we# dq 5 dq 4 v cc dq 12 nc ce 0 # a 13 a 14 a 12 a 15 ce 1 # 3/5# a 20 a 18 a 17 a 19 a 16 gnd dq 6 v cc dq 14 dq 15 ry/by# dq 7 oe# wp# dq 13 we# dq 5 dq 4 v cc dq 12 nc v pp a 11 a 10 rp# a 9 a 2 a 3 a 1 a 4 a 6 a 7 a 5 gnd v cc dq 9 a 8 dq 1 dq 0 a 0 dq 8 byte# nc dq 2 nc dq 10 dq 11 gnd dq 3 28f160s5 v pp a 11 a 10 rp# a 9 a 2 a 3 a 1 a 4 a 6 a 7 a 5 gnd v cc dq 9 a 8 dq 1 dq 0 a 0 dq 8 byte# nc dq 2 nc dq 10 dq 11 gnd dq 3 28f016sv 28f016sa 0606_04 note: 1. v cc (pin 42) and gnd (pin 15) are not internally connected. for future device revisions, it is recommended that these pins be connected to their respected power supplies (i.e., pin 42 = v cc and pin 15 = gnd). 2. for compatibility with future generations of intel strataflash memory, this nc (pin 23) should be connected to gnd figure 4. ssop lead configuration (64 mbit and 32 mbit) 2.0 principles of operation the intel strataflash memory devices include an on-chip wsm to manage block erase, program, and lock-bit configuration functions. it allows for 100% ttl-level control inputs, fixed power supplies during block erasure, program, lock-bit configuration, and minimal processor overhead with ram-like interface timings. after initial device power-up or return from reset/power-down mode (see bus operations), the device defaults to read array mode. manipulation of external memory control pins allows array read, standby, and output disable operations. read array, status register, query, and identifier codes can be accessed through the cui (command user interface) independent of the v pen voltage.
intel ? strataflash? memory technology, 32 and 64 mbit e 12 preliminary v penh on v pen enables successful block erasure, programming, and lock-bit configuration. all functions associated with altering memory contents block erase, program, lock-bit configurationare accessed via the cui and verified through the status register. commands are written using standard micro- processor write timings. the cui contents serve as input to the wsm, which controls the block erase, program, and lock-bit configuration. the internal algorithms are regulated by the wsm, including pulse repetition, internal verification, and margining of data. addresses and data are internally latched during program cycles. interface software that initiates and polls progress of block erase, program, and lock-bit configuration can be stored in any block. this code is copied to and executed from system ram during flash memory updates. after successful completion, reads are again possible via the read array command. block erase suspend allows system software to suspend a block erase to read or program data from/to any other block. 2.1 data protection depending on the application, the system desi gner may choose to make the v pen switchable (available only when memory block erases, programs, or lock- bit configurations are required) or hardwired to v penh . the device accommodates either design practice and encourages optimization of the processor-memory interface. when v pen v penlk , memory contents cannot be altered. the cuis two-step block erase, byte/word program, and lock-bit configuration command sequences provide protection from unwanted operations even when v penh is applied to v pen . all program functions are disabled when v cc is below the write lockout voltage v lko or when rp# is v il . the devices block locking capability provides additional protection from inadvertent code or data alteration by gating erase and program operations. 3.0 bus operation the local cpu reads and writes flash memory in-system. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 64-kword block 64-kword block 64-kword block 64-kword block 31 1 0 63 word wide (x16) mode 1fffff 1f0000 3fffff 3f0000 01ffff 010000 00ffff 000000 a [22-1]: 64-mbit a [21-1]: 32-mbit 128-kbyte block 128-kbyte block 128-kbyte block 128-kbyte block 31 1 0 63 byte-wide (x8) mode 3fffff 3e0000 7fffff 7e0000 03ffff 020000 01ffff 000000 a [22-0]: 64-mbit a [21-0]: 32-mbit 32-mbit 64-mbit 0606_05 figure 5. memory map
e intel ? strataflash? memory technology, 32 and 64 mbit 13 preliminary table 2. chip enable truth table (1,2) ce 2 ce 1 ce 0 device v il v il v il enabled v il v il v ih disabled v il v ih v il disabled v il v ih v ih disabled v ih v il v il enabled v ih v il v ih enabled v ih v ih v il enabled v ih v ih v ih disabled note: 1. see application note ap-647 intel strataflash? memory design guide for typical ce configurations. 2. for single-chip applications ce 2 and ce 1 can be strapped to gnd. 3.1 read information can be read from any block, query, identifier codes, or status register independent of the v pen voltage. rp# can be at either v ih or v hh . upon initial device power-up or after exit from reset/power-down mode, the device automatically resets to read array mode. otherwise, write the appropriate read mode command (read array, read query, read identifier codes, or read status register) to the cui. six control pins dictate the data flow in and out of the component: ce 0 , ce 1 , ce 2 , oe#, we#, and rp#. the device must be enabled (see table 2, chip enable truth table ), and oe# must be driven active to obtain data at the outputs. ce 0 , ce 1 , and ce 2 are the device selection controls and, when enabled (see table 2, chip enable truth table ), select the memory device. oe# is the data output (dq 0 Cdq 15 ) control and, when active, drives the selected memory data onto the i/o bus. we# must be at v ih . 3.2 output disable with oe# at a logic-high level (v ih ), the device outputs are disabled. output pins dq 0 Cdq 15 are placed in a high-impedance state. 3.3 standby ce 0 , ce 1 , and ce 2 can disable the device (see table 2, chip enable truth table ) and place it in standby mode which substantially reduces device power consumption. dq 0 Cdq 15 outputs are placed in a high-impedance state independent of oe#. if deselected during block erase, program, or lock-bit configuration, the wsm continues functioning, and consuming active power until the operation completes. 3.4 reset/power-down rp# at v il initiates the reset/power-down mode. in read modes, rp#-low deselects the memory, places output drivers in a high-impedance state, and turns off numerous internal circuits. rp# must be held low for a minimum of t plph . time t phqv is required after return from reset mode until initial memory access outputs are valid. after this wake- up interval, normal operation is restored. the cui is reset to read array mode and status register is set to 80h. during block erase, program, or lock-bit configuration modes, rp#-low will abort the operation. in default mode, sts transitions low and remains low for a maximum time of t plph + t phrh until the reset operation is complete. memory contents being altered are no longer valid; the data may be partially corrupted after a program or partially altered after an erase or lock-bit configuration. time t phwl is required after rp# goes to logic-high (v ih ) before another command can be written. as with any automated device, it is important to assert rp# during system reset. w hen the system comes out of reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase, program, or lock-bit configuration modes. if a cpu reset occurs with no flash memory reset, proper initialization may not occur because the flash memory may be providing status information instead of array data. intels flash memories allow proper initialization following a system reset thr ough the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu.
intel ? strataflash? memory technology, 32 and 64 mbit e 14 preliminary 3.5 read query the read query operation outputs block status information, cfi (common flash interface) id string, system interface information, device geometry information, and intel-specific extended query information. 3.6 read identifier codes the read identifier codes operation outputs the manufacturer code, device code, block lock configuration codes for each block, and the master lock configuration code (see figure 6). using the manufacturer and device codes, the system cpu can automatically match the device with its proper algorithms. the block lock and master lock configuration codes identify locked and unlocked blocks and master lock-bit setting. 3.7 write writing commands to the cui enables reading of device data, query, identifier codes, inspection and clearing of the status register, and, when v pen = v penh , block erasure, program, and lock-bit configuration. the block erase command requires appropriate command data and an address within the block to be erased. the byte/word program command requires the command and address of the location to be written. set master and block lock-bit commands require the command and address within the device (master lock) or block within the device (block lock) to be locked. the clear block lock-bits command requires the command and address within the device. the cui does not occupy an addressable memory location. it is written when the device is enabled and we# is active. the address and data needed to execute a command are latched on the rising edge of we# or the first edge of ce 0 , ce 1 , or ce 2 that disables the device (see table 2, chip enable truth table ). standard microprocessor write timings are used. 4.0 command definitions when the v pen voltage v penlk , only read operations from the status register, query, identifier codes, or blo cks are enabled. placing v penh on v pen additionally enables block erase, program, and lock-bit configuration operations. device operations are selected by writing specific commands into the cui. table 4 defines these commands. reserved for future implementation reserved for future implementation (blocks 32 through 62) reserved for future implementation reserved for future implementation (blocks 2 through 30) reserved for future implementation reserved for future implementation block 63 block 31 block 1 block 0 lock configuration reserved for future implementation block 0 master lock configuration manufacturer code device code 3fffff 3f0003 3f0002 3f0000 3effff 1effff 1f0003 1f0002 1f0000 01ffff 010003 010002 010000 00ffff 000004 000003 000002 000001 000000 32 mbit 64 mbit word address a[22-1]: 64 mbit a[21-1]: 32 mbit block 31 lock configuration block 63 lock configuration block 1 lock configuration 0606_06 note: a 0 is not used in either x8 or x16 modes when obtaining these identifier codes. data is always given on the low byte in x16 mode (upper byte contains 00h). figure 6. device identifier code memory map
e intel ? strataflash? memory technology, 32 and 64 mbit 15 preliminary table 3. bus operations mode notes rp# ce 0,1,2 (10) oe# (11) we# (11) address v pen dq (8) sts (default mode) read array 1,2,3 v ih or v hh enabled v il v ih xx d out high z (9) output disable v ih or v hh enabled v ih v ih x x high z x standby v ih or v hh disabled x x x x high z x reset/power- down mode v il x x x x x high z high z (9) read identifier codes v ih or v hh enabled v il v ih see figure 6 x note 4 high z (9) read query v ih or v hh enabled v il v ih see table 7 x note 5 high z (9) read status (wsm off) v ih or v hh enabled v il v ih xx d out read status (wsm on) v ih or v hh enabled v il v ih xv penh dq 7 = d out dq 15 C8 = high z dq 6C0 = high z write 3,6,7 v ih or v hh enabled v ih v il xx d in x notes: 1. refer to dc characteristics . when v pen v penlk , memory contents can be read, but not altered. 2. x can be v il or v ih for control and address pins, and v penlk or v penh for v pen . see dc characteristics for v penlk and v penh voltages. 3. in default mode, sts is v ol when the wsm is executing internal block erase, program, or lock-bit configuration algorithms. it is v oh when the wsm is not busy, in block erase suspend mode (with programming inactive), or reset/power-down mode. 4. see read identifier codes command section for read identifier code data. 5. see read query mode command section for read query data. 6. command writes involving block erase, program, or lock-bit configuration are reliably executed when v pen = v penh and v cc is within specification. block erase, program, or lock-bit configuration with v ih < rp# < v hh produce spurious results and should not be attempted. 7. refer to table 4 for valid d in during a write operation. 8. dq refers to dq 0 Cdq 7 if byte# is low and dq 0 Cdq 15 if byte# is high. 9. high z will be v oh with an external pull-up resistor. 10. see table 2 for valid ce configurations. 11. oe# and we# should never be enabled simultaneously.
intel ? strataflash? memory technology, 32 and 64 mbit e 16 preliminary table 4. intel ? strataflash? memory command set definitions (14) command scaleable or basic command set (15) bus cycles req'd. notes first bus cycle second bus cycle oper (1) addr (2) data (3,4) oper (1) addr (2) data (3,4) read array scs/bcs 1 write x ffh read identifier codes scs/bcs 3 2 5 write x 90h read ia id read query scs 3 2 write x 98h read qa qd read status register scs/bcs 2 6 write x 70h read x srd clear status register scs/bcs 1 write x 50h write to buffer scs/bcs > 2 7,8,9 write ba e8h write ba n word/byte program scs/bcs 2 10,11 write pa 40h or 10h write pa pd block erase scs/bcs 2 9,10 write ba 20h write ba d0h block erase suspend scs/bcs 1 9,10 write x b0h block erase resume scs/bcs 1 10 write x d0h configuration scs 2 write x b8h write x cc set block lock-bit scs 2 12 write ba 60h write ba 01h clear block lock- bits scs 2 13 write x 60h write x d0h set master lock- bit 2 12,13 write x 60h write x f1h
e intel ? strataflash? memory technology, 32 and 64 mbit 17 preliminary notes: 1. bus operations are defined in table 3. 2. x = any valid address within the device. ba = address within the block. ia = identifier code address: see figure 6 and table 13. qa = query database address. pa = address of memory location to be programmed. 3. id = data read from identifier codes. qd = data read from query database. srd = data read from status register. see table 16 for a description of the status register bits. pd = data to be programmed at location pa. data is latched on the rising edge of we#. cc = configuration code. 4. the upper byte of the data bus (dq 8 Cdq 15 ) during command writes is a dont care in x16 operation. 5. following the read identifier codes command, read operations access manufacturer, device, block lock, and master lock codes. see read identifier codes command section for read identifier code data. 6. if the wsm is running, only dq 7 is valid; dq 15 Cdq 8 and dq 6 Cdq 0 float, which places them in a high-impedance state. 7. after the write to buffer command is issued check the xsr to make sure a buffer is available for writing. 8. the number of bytes/words to be written to the write buffer = n + 1, where n = byte/word count argument. count ranges on this device for byte mode are n = 00h to n = 1fh and for word mode are n = 0000h to n = 000fh. the third and consecutive bus cycles, as determined by n, are for writing data into the write buffer. the confirm command (d0h) is expected after exactly n + 1 write cycles; any other command at that point in the sequence aborts the write to buffer operation. please see figure 7, write to buffer flowchart , for additional information. 9. programming the write buffer to flash or initiating the erase operation does not begin until a confirm command (d0h) is issued. 10. if the block is locked, rp# must be at v hh to enable block erase or program operations. attempts to issue a block erase or program to a locked block while rp# is v ih will fail. 11. either 40h or 10h are recognized by the wsm as the byte/word program setup. 12. if the master lock-bit is set, rp# must be at v hh to set a block lock-bit. rp# must be at v hh to set the master lock-bit. if the master lock-bit is not set, a block lock-bit can be set while rp# is v ih . 13. if the master lock-bit is set, rp# must be at v hh to clear block lock-bits. the clear block lock-bits operation simultaneously clears all block lock-bits. if the master lock-bit is not set, the clear block lock-bits command can be done while rp# is v ih . 14. commands other than those shown above are reserved by intel for future device implementations and should not be used. 15. the basic command set (bcs) is the same as the 28f008sa command set or intel standard command set. the scaleable command set (scs) is also referred to as the intel extended command set.
intel ? strataflash? memory technology, 32 and 64 mbit e 18 preliminary 4.1 read array command upon initial device power-up and after exit from reset/power-down mode, the device defaults to read array mode. this operation is also initiated by writing the read array command. the device remains enabled for reads until another command is written. once the internal wsm has started a block erase, program, or lock-bit configuration, the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via an erase suspend command. the read array command functions independently of the v pen voltage and rp# can be v ih or v hh . 4.2 read query mode command this section defines the data structure or database returned by the scs (scaleable command set) query command. system software should parse this structure to gain critical information to enable programming, block erases, and otherwise control the flash component. the scs query is part of an overall specification for multiple command set and control interface descriptions called common flash interface, or cfi. the query can only be accessed when the wsm is off or the device is suspended. 4.2.1 query structure output the query database, described later, allows system software to gain critical information for controlling the flash component. this section describes the devices cfi-compliant interface that allows the host system to access query data. query data are always presented on the lowest- order data outputs dq 0 Cdq 7 only. the query table device starting address is a 10h word address. the first two bytes of the query structure, q and r in ascii, appear on the low byte at word addresses 10h and 11h. this cfi-compliant device outputs 00h data on upper bytes. thus, the device outputs ascii q in the low byte dq 0 Cdq 7 and 00h in the high byte dq 8 Cdq 15 . since the device is x8/x16 capable, the x8 data is still presented in word-relative (16-bit) addresses. however, the fill data (00h) is not the same as driven by the upper bytes in the x16 mode. as in x16 mode, the byte address (a 0 or a 1 depending on pinout) is ignored for query output so that the odd byte address (a 0 or a 1 high) repeats the even byte address data (a 0 or a 1 low). therefore, in x8 mode using byte addressing, the device will output the sequence q, q, r, r, y, y, and so on, beginning at byte-relative address 20h (which is equivalent to word offset 10h in x16 mode). in query addresses where two or more bytes of information are located, the least significant data byte is presented on the lower address, and the most significant data byte is presented on the higher address.
e intel ? strataflash? memory technology, 32 and 64 mbit 19 preliminary table 5. summary of query structure output as a function of device and mode device type/ mode query start location in maximum device bus width addresses query data with maximum device bus width addressing x = ascii equivalent query start address in bytes query data with byte addressing x16 device/ x16 mode 10h 10h: 0051h q 11h: 0052h r 12h: 0059h y 20h 20h: 51h q 21h: 00h null 22h: 52h r x16 device/ x8 mode n/a (1) n/a (1) 20h 20h: 51h q 21h: 51h q 22h: 52h r note: 1. the system must drive the lowest order addresses to access all the devices array data when the device is configured in x8 mode. therefore, word addressing where these lower addresses not toggled by the system is not applicable for x8- configured devices. table 6. example of query structure output of a x16- and x8-capable device device address word addressing: query data byte address byte addressing: query data a 16 Ca 1 d 15 Cd 0 a 7 Ca 0 d 7 Cd 0 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h ... 0051h q 0052h r 0059h y p_id lo prvendor p_id hi id # p lo prvendor p hi tbladr a_id lo altvendor a_id hi id # ... 20h 21h 22h 23h 24h 25h 26h 27h 28h ... 51h q 51h q 52h r 52h r 59h y 59h y p_id lo prvendor p_id lo id # p_id hi ...
intel ? strataflash? memory technology, 32 and 64 mbit e 20 preliminary 4.2.2 query structure overview the query command causes the flash component to display the common flash interface (cfi) query structure or database. the structure sub-sections and address locations are summarized below. see ap- 646 common flash interface (cfi) and command sets (order number 292204) for a full description of cfi. the following sections describe the query structure sub-sections in detail. table 7. query structure offset sub-section name description 00h manufacturer code 01h device code (ba+2)h (2) block status register block-specific information 04C0fh reserved reserved for vendor-specific information 10h cfi query identification string command set id and vendor data offset 1bh system interface information device timing and voltage information 27h device geometry definition flash device layout p (3) primary vendor-specific extended query table vendor-defined additional information specific to the primary vendor algorithm notes: 1. refer to query data output section of device hardware interface for the detailed definition of offset address as a function of device word width and mode. 2. ba = the beginning location of a block address (i.e., 2000h is the beginning location of block 2 when the block size is 128 kb). 3. the primary vendor-specific extended query table (p) address may change among scs-compliant devices. software should retrieve this address from address 15 to guarantee compatibility with future scs-compliant devices.
e intel ? strataflash? memory technology, 32 and 64 mbit 21 preliminary 4.2.3 block status register the block status register indicates whether a given block is locked and can be accessed for program/erase operations. the block status register is accessed from word address 02h within each block. table 8. block status register offset length (bytes) description intel ? strataflash? memory x16 device/mode (ba +2)h 1 01h block status register ba+2: 0000h or 0001h bsr.0 = block lock status (optional) 1 = locked 0 = unlocked ba+2 (bit 0): 0 or 1 bsr.1 = block erase status (2) (optional) 1 = last erase operation did not complete successfully 0 = last erase operation completed successfully ba+2 (bit 1): 0 (the device does not support block erase status) bsr 2 C7 reserved for future use ba+2 (bits 2C7): 0 notes: 1. ba = the beginning location of a block address (i.e., 2000h is the beginning location of block 2). 2. block erase status is an optional part of the scs definition and is not incorporated on this device.
intel ? strataflash? memory technology, 32 and 64 mbit e 22 preliminary 4.2.4 cfi query identification string the identification string provides verification that the component supports the common flash interface specification. additionally, it indicates which version of the spec and which vendor-specified command set(s) is(are) supported. table 9. cfi identification offset length (bytes) description intel? strataflash? memory 10h 03h query-unique ascii string qry 10: 0051h 11: 0052h 12: 0059h 13h 02h primary vendor command set and control interface id code 16-bit id code for vendor-specified algorithms 13: 0001h 14: 0000h 15h 02h address for primary algorithm extended query table offset value = p = 31h 15: 0031h 16: 0000h 17h 02h alternate vendor command set and control interface id code second vendor-specified algorithm supported note: 0000h means none exists 17: 0000h 18: 0000h 19h 02h address for secondary algorithm extended query table note: 0000h means none exists 19: 0000h 1a: 0000h
e intel ? strataflash? memory technology, 32 and 64 mbit 23 preliminary 4.2.5 system interface information the following device information can optimize system interface software. table 10. system interface information offset length (bytes) description intel ? strataflash? memory 1bh 01h v cc logic supply minimum program/erase voltage bits 7 C4 bcd volts bits 3C0 bcd 100 mv 1b: 0045h 1ch 01h v cc logic supply maximum program/erase voltage bits 7C4 bcd volts bits 3C0 bcd 100 mv 1c: 0055h 1dh 01h v pp [programming] supply minimum program/erase voltage bits 7C4 hex volts bits 3C0 bcd 100 mv 1d: 0000h 1eh 01h v pp [programming] supply maximum program/erase voltage bits 7C4 hex volts bits 3C0 bcd 100 mv 1e: 0000h 1fh 01h typical time-out per single byte/word program, 2 n s 1f: 0007h 20h 01h typical time-out for max. buffer write, 2 n s 20: 0007h 21h 01h typical time-out per individual block erase, 2 n ms 21: 000ah 22h 01h typical time-out for full chip erase, 2 n ms ( 0000h = not supported ) 22: 0000h 23h 01h maximum time-out for byte/word program, 2 n times typical 23: 0004h 24h 01h maximum time-out for buffer write, 2 n times typical 24: 0004h 25h 01h maximum time-out per individual block erase, 2 n times typical 25: 0004h 26h 01h maximum time-out for chip erase, 2 n times typical ( 00h = not supported ) 26: 0000h
intel ? strataflash? memory technology, 32 and 64 mbit e 24 preliminary 4.2.6 device geometry definition this field provides critical details of the flash device geometry. table 11. device geometry definition offset length (bytes) description intel ? strataflash? memory 27h 01h device size = 2 n in number of bytes. 27: 0017h (64-mbit) 27: 0016h (32-mbit) 28h 02h flash device interface description value meaning 0000h x8 asynchronous 0002h x8/x16 asynchronous 28: 0002h 29: 0000h 2ah 02h maximum number of bytes in write buffer = 2 n 2a: 0005h 2b: 0000h 2ch 01h number of erase block regions within device: bits 7C0 = x = # of erase block regions 2c: 0001h 2dh 04h erase block region information bits 15C0 = y , where y+1 = number of erase blocks of identical size within region bits 31C16 = z , where the erase block(s) within this region are (z) times 256 bytes y: 64 blocks (64-mbit) 2d: 003fh 2e: 0000h y: 32 blocks (32-mbit) 2d: 001fh 2e: 0000h z: (128 kb size) 2f: 0000h 30: 0002h
e intel ? strataflash? memory technology, 32 and 64 mbit 25 preliminary 4.2.7 primary-vendor specific extended query table certain flash features and commands are optional. the primary vendor-specific extended query table specifies this and other similar information. table 12. primary vendor-specific extended query offset (1) length (bytes) description intel ? strataflash? memory (p)h 03h primary extended query table unique ascii string pri 31: 0050h 32: 0052h 33: 0049h (p +3)h 01h major version number, ascii 34: 0031 (p +4)h 01h minor version number, ascii 35: 0031 (p +5)h 04h optional feature and command support bit 0 chip erase supported (1=yes, 0=no ) bit 1 suspend erase supported ( 1=yes , 0=no) bit 2 suspend program supported (1=yes, 0=no ) bit 3 lock/unlock supported ( 1=yes , 0=no) bit 4 queued erase supported (1=yes, 0=no ) bits 5 C31 reserved for future use; undefined bits are 0 36: 000ah 37: 0000h 38: 0000h 39: 0000h (p +9)h 01h supported functions after suspend read array, status, and query are always supported during suspended erase. this field defines other operations supported. bit 0 program supported after erase suspend ( 1=yes , 0=no) bits 1C7 reserved for future use; undefined bits are 0 3a: 0001h (p +a)h 02h block status register mask defines which bits in the block status register section of query are implemented. bit 0 block status register lock bit [bsr.0] active ( 1=yes , 0=no) bit 1 block status register valid bit [bsr.1] active (1=yes, 0=no ) bits 2C15 reserved for future use; undefined bits are 0 3b: 0001h 3c: 0000h note: 1. the primary vendor-specific extended query table (p) address may change among scs-compliant devices. software should retrieve this address from address 15 to guarantee compatibility with future scs-compliant devices.
intel ? strataflash? memory technology, 32 and 64 mbit e 26 preliminary table 12. primary vendor-specific extended query (continued) offset (1) length (bytes) description intel ? strataflash? memory (p +c)h 01h v cc optimum program/erase voltage (highest performance) bits 7 C4 bcd value in volts bits 3C0 bcd value in 100 millivolts 3d: 0050h (p +d)h 01h v pp [programming] optimum program/erase voltage bits 7C4 hex value in volts bits 3C0 bcd value in 100 millivolts note: this value is 0000h; no v pp pin is present 3e: 0000h (p +e)h reserved reserved for future use note: 1. the primary vendor-specific extended query table (p) address may change among scs-compliant devices. software should retrieve this address from address 15 to guarantee compatibility with future scs-compliant devices. 4.3 read identifier codes command the identifier code operation is initiated by writing the read identifier codes command. following the command write, read cycles from addresses shown in figure 6 retrieve the manufacturer, device, block lock configuration and master lock configuration codes (see table 13 for identifier code values). to terminate the operation, write another valid command. like the read array command, the read identifier codes command functions independently of the v pen voltage and rp# can be v ih or v hh . this command is valid only when the wsm is off or the device is suspended. following the read identifier codes command, the following information can be read: table 13. identifier codes (1) code address (1) data manufacture code 00000 (00) 89 device code 32-mbit 00001 (00) 14 64-mbit 00001 (00) 15 block lock configuration x 0002 (2) block is unlocked dq 0 = 0 block is locked dq 0 = 1 reserved for future use dq 1 C7 master lock configuration 00003 device is unlocked dq 0 = 0 device is locked dq 0 = 1 reserved for future use dq 1C7 note: 1. a 0 is not used in either x8 or x16 modes when obtaining the identifier codes. the lowest order address line is a 1 . data is always presented on the low byte in x16 mode (upper byte contains 00h). 2. x selects the specific blocks lock configuration code. see figure 6 for the device identifier code memory map.
e intel ? strataflash? memory technology, 32 and 64 mbit 27 preliminary 4.4 read status register command the status register may be read to determine when a block erase, program, or lock-bit configuration is complete and whether the operation completed successfully. it may be read at any time by writing the read status register command. after writing this command, all subsequent read operations output data from the status register until another valid command is written. the status register contents are latched on the falling edge of oe# or the first edge of ce 0 , ce 1 , or ce 2 that enables the device (see table 2, chip enable truth table ). oe# must toggle to v ih or the device must be disabled (see table 2, chip enable truth table ) before further reads to update the status register latch. the read status register command functions independently of the v pen voltage. rp# can be v ih or v hh . during a program, block erase, set lock-bit, or clear lock-bit command sequence, only sr.7 is valid until the write state machine completes or suspends the operation. device i/o pins dq 0 Cdq 6 and dq 8 C dq 15 are placed in a high-impedance state. when the operation completes or suspends (check status register bit 7), all contents of the status register are valid when read. 4.5 clear status register command status register bits sr.5, sr.4, sr.3, and sr.1 are set to 1s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 16). by allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. the status register may be polled to determine if an error occurred during the sequence. to clear the status register, the clear status register command (50h) is written. it functions independently of the applied v pen voltage. rp# can be v ih or v hh . the clear status register command is only valid when the wsm is off or the device is suspended. 4.6 block erase command erase is executed one block at a time and initiated by a two-cycle comm and. a block erase setup is first written, followed by an block erase confirm. this command sequence requires an appropriate address within the block to be erased (erase changes all block data to ffh). block preconditioning, erase, and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase s equence is written, the device automatically outputs status register data when read (see figure 9). the cpu can detect block erase completion by analyzing the output of the sts pin or status register bit sr.7. toggle oe#, ce 0 , ce 1 , or ce 2 to update the status register. when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to 1. also, reliable block erasure can only occur when v cc is valid and v pen = v penh . if block erase is attempted while v pen v penlk , sr.3 and sr.5 will be set to 1. successful block erase requires that the corresponding block lock-bit be cleared or, if set, that rp# = v hh . if block erase is attempted when the corresponding block lock-bit is set and rp# = v ih , sr.1 and sr.5 will be set to 1. block erase operations with v ih < rp# < v hh produce spurious results and should not be attempted. 4.7 block erase suspend command the block erase suspend command allows block-erase interruption to read or program data in another block of memory. once the block erase process starts, writing the block erase suspend command requests that the wsm suspend the block erase sequence at a predetermined point in the algorithm. the device outputs status register data when read after the block erase suspend command is written. polling status register bit sr.7 then sr.6 can determine when the block erase operation has been suspended (both will be set to 1). in default mode, sts will also transition to
intel ? strataflash? memory technology, 32 and 64 mbit e 28 preliminary v oh . specification t whrh defines the block erase suspend latency. at this point, a read array command can be written to read data from blo cks other t han that which is suspended. a program command sequence can also be issued during erase suspend to program data in other blocks. during a program operation with block erase suspended, status register bit sr.7 will return to 0 and the sts output (in default mode) will transition to v ol . the only other valid commands while block erase is suspended are read query, read status register, clear status register, configure, and block erase resume. after a block erase resume command is written to the flash memory, the wsm will continue the block erase process. status register bits sr.6 and sr.7 will automatically clear and sts (in default mode) will return to v ol . after the erase resume command is written, the device automatically outputs status register data when read (see figure 10). v pen must remain at v penh (the same v pen level used for block erase) while block erase is suspended. rp# must also remain at v ih or v hh (the same rp# level used for block erase). block erase cannot resume until program operations initiated during block erase suspend have completed. 4.8 write to buffer command to program the flash device, a write to buffer command sequence is initiated. a variable number of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. first, the write to buffer setup command is issued along with the block address (see figure 7, write to buffer flowchart ). at this point, the extended status register (xsr, see table 17) information is loaded and xsr.7 reverts to "buffer available" status. if xsr.7 = 0, the write buffer is not available. to retry, continue monitoring xsr.7 by issuing the write to buffer setup command with the block address until xsr.7 = 1. when xsr.7 transitions to a 1, the buffer is ready for loading. now a word/byte count is given to the part with the block address. on the next write, a device start address is given along with the write buffer data. subsequent writes provide additional device addresses and data, depending on the count. all subsequent addresses must lie within the start address plus the count. internally, this device programs many flash cells in parallel. because of this parallel programming, maximum programming performance and lower power are obtained by aligning the start address at the beginning of a write buffer boundary (i.e., a 4 Ca 0 of the start address = 0). after the final buffer data is given, a write confirm command is issued. this initiates the wsm (write state machine) to begin copying the buffer data to the flash array. if a command other than write confirm is written to the device, an invalid command/sequence error will be generated and status register bits sr.5 and sr.4 will be set to a 1. for additional buffer writes, issue another write to buffer setup command and check xsr.7. if an error occurs while writing, the device will stop writing, and status register bit sr.4 will be set to a 1 to indicate a program failure. the internal wsm verify only detects errors for 1s that do not successfully program to 0s. if a program error is detected, the status register should be cleared. any time sr.4 and/or sr.5 is set (e.g., a media failure occurs during a program or an erase), the device will not accept any more write to buffer commands. additionally, if the user attempts to program past an erase block boundary with a write to buffer command, the device will abort the write to buffer operation. this will generate an "invalid command/ sequence" error and status register bits sr.5 and sr.4 will be set to a 1. reliable buffered writes can only occur when v pen = v penh . if a buffered write is attempted while v pen v penlk , status register bits sr.4 and sr.3 will be set to 1. buffered write attempts with invalid v cc and v pen voltages produce spurious results and should not be attempted. finally, successful programming requires that the corresponding block lock-bit be reset or, if set, that rp# = v hh . if a buffered write is attempted when the corresponding block lock-bit is set and rp# = v ih , sr.1 and sr.4 will be set to 1. buffered write operations with v ih < rp# < v hh produce spurious results and should not be attempted. 4.9 byte/word program commands byte/word program is executed by a two-cycle command sequence. byte/word program setup (standard 40h or alternate 10h) is written followed by a second write that specifies the address and data (latched on the rising edge of we#). the wsm
e intel ? strataflash? memory technology, 32 and 64 mbit 29 preliminary then takes over, controlling the program and program verify algorithms internally. after the program sequence is written, the device automatically outputs status register data when read (see figure 8). the cpu can detect the completion of the program event by analyzing the sts pin or status register bit sr.7. when program is complete, status register bit sr.4 should be checked. if a program error is detected, the status register should be cleared. the internal wsm verify only detects errors for 1s that do not successfully program to 0s. the cui remains in read status register mode until it receives another command. reliable byte/word programs can only occur when v cc and v pen are valid. if a byte/word program is attempted while v pen v penlk , status register bits sr.4 and sr.3 will be set to 1. successful byte/word programs require that the corresponding block lock-bit be cleared or, if set, that rp# = v hh . if a byte/word program is attempted when the corresponding block lock-bit is set and rp# = v ih , sr.1 and sr.4 will be set to 1. byte/word program operations with v ih < rp# < v hh produce spurious results and should not be attempted. 4.10 configuration command the status (sts) pin can be configured to different states using the configuration command. once the sts pin has been configured, it remains in that configuration until another configuration command is issued or rp# is asserted low. initially, the sts pin defaults to ry/by# operation where ry/by# low indicates that the state machine is busy. ry/by# high indicates that the state machine is ready for a new operation or suspended. table 15 displays the possible sts configurations. to reconfigure the status (sts) pin to other modes, the configuration command is given followed by the desired configuration code. the three alternate configurations are all pulse mode for use as a system interrupt as descri bed below. for these configurations, bit 0 controls erase complete interrupt pulse, and bit 1 controls program complete interrupt pulse. supplying the 00h configuration code with the configuration command resets the sts pin to the default ry/by# level mode. the possible configurations and their usage are described in table 15. the configuration command may only be given when the device is not busy or suspended. check sr.7 for device status. an invalid configuration code will result in both status register bits sr.4 and sr.5 being set to 1. when configured in one of the pulse modes, the sts pin pulses low with a typical pulse width of 250 ns. 4.11 set block and master lock-bit commands a flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a master lock-bit. the block lock-bits gate program and erase operations while the master lock-bit gates block-lock bit modification. with the master lock-bit not set, individual block lock-bits can be set using the set block lock-bit command. the set master lock-bit command, in conjunction with rp# = v hh , sets the master lock-bit. after the master lock-bit is set, subsequent setting of block lock-bits requires both the set block lock-bit command and v hh on the rp# pin. these commands are invalid while the wsm is running or the device is suspended. see table 14 for a summary of hardware and software write protection options. set block lock-bit and master lock-bit commands are executed by a two-cycle s equence. the set block or master lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set master lock-bit confirm (and any device address). the wsm then controls the set lock-bit algorithm. after the sequence is written, the device automatically outputs status register data when read (see figure 11). the cpu can detect the completion of the set lock-bit event by analyzing the sts pin output or status register bit sr.7. when the set lock-bit operation is complete, status register bit sr.4 should be checked. if an error is detected, the status register should be cleared. the cui will remain in read status register mode until a new command is issued. this two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. an invalid set block or master lock-bit command will result in status register bits sr.4 and sr.5 being set to 1. also, reliable operations occur only when v cc and v pen are valid. with v pen v penlk , lock-bit contents are protected against alteration.
intel ? strataflash? memory technology, 32 and 64 mbit e 30 preliminary a successful set block lock-bit operation requires that the master lock-bit be zero or, if the master lock-bit is set, that rp# = v hh . if it is attempted with the master lock-bit set and rp# = v ih , sr.1 and sr.4 will be set to 1 and the operation will fail. set block lock-bit operations while v ih < rp# < v hh produce spurious results and should not be attempted. a successful set master lock-bit operation requires that rp# = v hh . if it is attempted with rp# = v ih , sr.1 and sr.4 will be set to 1 and the operation will fail. set master lock-bit operations with v ih < rp# < v hh produce spurious results and should not be attempted. 4.12 clear block lock-bits command all set block lock-bits are cleared in parallel via the clear block lock-bits command. with the master lock-bit not set, block lock-bits can be cleared using only the clear block lock-bits command. if the master lock-bit is set, clearing block lock-bits requires both the clear block lock-bits command and v hh on the rp# pin. this command is invalid while the wsm is running or the device is suspended. see table 14 for a summary of hardware and software write protection options. clear block lock-bits command is executed by a two-cycle s equence. a clear block lock-bits setup is first written. the device automatically outputs status register data when read (see figure 12). the cpu can detect completion of the clear block lock-bits event by analyzing the sts pin output or status register bit sr.7. when the operation is complete, status register bit sr.5 should be checked. if a clear block lock-bit error is detected, the status register should be cleared. the cui will remain in read status register mode until another command is issued. this two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. an invalid clear block lock-bits command sequence will result in status register bits sr.4 and sr.5 being set to 1. also, a reliable clear block lock-bits operation can only occur when v cc and v pen are valid. if a clear block lock-bits operation is attempted while v pen v penlk , sr.3 and sr.5 will be set to 1. a successful clear block lock-bits operation requires that the master lock-bit is not set or, if the master lock-bit is set, that rp# = v hh . if it is attempted with the master lock-bit set and rp# = v ih , sr.1 and sr.5 will be set to 1 and the operation will fail. a clear block lock-bits operation with v ih < rp# < v hh produce spurious results and should not be attempted. if a clear block lock-bits operation is aborted due to v pen or v cc transitioning out of valid range or rp# active transition, block lock-bit values are left in an undetermined state. a repeat of clear block lock- bits is required to initialize block lock-bit contents to known values. once the master lock-bit is set, it cannot be cleared. table 14. write protection alternatives operation master lock-bit block lock-bit rp# effect block erase or 0 v ih or v hh block erase and program enabled program x 1 v ih block is locked. block erase and program disabled v hh block lock-bit override. block erase and program enabled set or clear block 0 x v ih or v hh set or clear block lock-bit enabled lock-bit 1 x v ih master lock-bit is set. set or clear block lock-bit disabled v hh master lock-bit override. set or clear block lock-bit enabled set master x x v ih set master lock-bit disabled lock-bit v hh set master lock-bit enabled
e intel ? strataflash? memory technology, 32 and 64 mbit 31 preliminary table 15. configuration coding definitions reserved pulse on program complete (1) pulse on erase complete (1) bits 7 C2 bit 1 bit 0 dq 7 Cdq 2 = reserved dq 1 Cdq 0 = sts pin configuration codes 00 = default, level mode ry/by# (device ready) indication 01 = pulse on erase complete 10 = pulse on program complete 11 = pulse on erase or program complete configuration codes 01b, 10b, and 11b are all pulse mode such that the sts pin pulses low then high when the operation indicated by the given configuration is completed. configuration command sequences for sts pin configuration (masking bits dq 7 Cdq 2 to 00h) are as follows: default ry/by# level mode: b8h, 00h er int (erase interrupt): b8h, 01h pulse-on-erase complete pr int (program interrupt): b8h, 02h pulse-on-program complete er/pr int (erase or program interrupt): b8h, 03h pulse-on-erase or program complete dq 7 Cdq 2 are reserved for future use. default (dq 1 Cdq 0 = 00) ry/by#, level mode used to control hold to a memory controller to prevent accessing a flash memory subsystem while any flash device's wsm is busy. configuration 01 er int, pulse mode used to generate a system interrupt pulse when any flash device in an array has completed a block erase or sequence of queued block erases. helpful for reformatting blocks after file system free space reclamation or cleanup configuration 10 pr int, pulse mode used to generate a system interrupt pulse when any flash device in an array has complete a program operation. provides highest performance for servicing continuous buffer write operations. configuration 11 er/pr int, pulse mode used to generate system interrupts to trigger servicing of flash arrays when either erase or program operations are completed when a common interrupt service routine is desired. note: 1. when the device is configured in one of the pulse modes, the sts pin pulses low with a typical pulse width of 250 ns.
intel ? strataflash? memory technology, 32 and 64 mbit e 32 preliminary table 16. status register definitions wsms ess eclbs pslbs vpens r dps r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 high z when busy? status register bits notes: no yes yes yes yes yes yes yes sr.7 = write state machine status 1 = ready 0 = busy sr.6 = erase suspend status 1 = block erase suspended 0 = block erase in progress/completed sr.5 = erase and clear lock-bits status 1 = error in block erasure or clear lock-bits 0 = successful block erase or clear lock-bits sr.4 = program and set lock-bit status 1 = error in programming or set master/block lock-bit 0 = successful programming or set master/block lock bit sr.3 = programming voltage status 1 = low programming voltage detected, operation aborted 0 = programming voltage ok sr.2 = reserved for future enhancements sr.1 = device protect status 1 = master lock-bit, block lock-bit and/or rp# lock detected, operation abort 0 = unlock sr.0 = reserved for future enhancements check sts or sr.7 to determine block erase, program, or lock-bit configuration completion. sr.6 Csr.0 are not driven while sr.7 = 0. if both sr.5 and sr.4 are 1s after a block erase or lock-bit configuration attempt, an improper command sequence was entered. sr.3 does not provide a continuous programming voltage level indication. the wsm interrogates and indicates the programming voltage level only after block erase, program, set block/master lock-bit, or clear block lock-bits command sequences. sr.1 does not provide a continuous indication of master and block lock-bit values. the wsm interrogates the master lock-bit, block lock-bit, and rp# only after block erase, program, or lock-bit configuration command sequences. it informs the system, depending on the attempted operation, if the block lock-bit is set, master lock-bit is set, and/or rp# is not v hh . read the block lock and master lock configuration codes using the read identifier codes command to determine master and block lock-bit status. sr.2 and sr.0 are reserved for future use and should be masked when polling the status register.
e intel ? strataflash? memory technology, 32 and 64 mbit 33 preliminary table 17. extended status register definitions wbs reserved bit 7 bits 6 C0 high z when busy? status register bits notes: no yes xsr.7 = write buffer status 1 = write buffer available 0 = write buffer not available xsr.6 Cxsr.0 = reserved for future enhancements after a buffer-write command, xsr.7 = 1 indicates that a write buffer is available. sr.6Csr.0 are reserved for future use and should be masked when polling the status register.
intel ? strataflash? memory technology, 32 and 64 mbit e 34 preliminary start write word or byte count, block address write buffer data, start address x = 0 x = x + 1 write next buffer data, device address abort write to buffer command? check x = n? another write to buffer? read status register sr.7 = programming complete read extended status register xsr.7 = 1 no yes no no 1 write to buffer aborted yes no yes full status check if desired program buffer to flash confirm d0h issue write to buffer command e8h, block address write to another block address write to buffer time-out? 0 set time-out issue read status command yes bus operation command comments write write to buffer data = e8h block address read xsr. 7 = valid addr = block address standby check xsr. 7 1 = write buffer available 0 = write buffer not available write (note 1, 2) data = n = word/byte count n = 0 corresponds to count = 1 addr = block address write (note 3, 4) data = write buffer data addr = device start address write (note 5, 6) data = write buffer data addr = device address write program buffer to flash confirm data = d0h addr = block address read status register data with the device enabled, oe# low updates sr addr = block address standby check sr.7 1 = wsm ready 0 = wsm busy 1. byte or word count values on dq 0 -dq 7 are loaded into the count register. count ranges on this device for byte mode are n = 00h to 1fh and for word mode are n = 0000h to 000fh. 2. the device now outputs the status register when read (xsr is no longer available). 3. write buffer contents will be programmed at the device start address or destination flash address. 4. align the start address on a write buffer boundary for maximum programming performance (i.e., a 4 - a 0 of the start address = 0). 5. the device aborts the write to buffer command if the current address is outside of the original block address. 6. the status register indicates an "improper command sequence" if the write to buffer command is aborted. follow this with a clear status register command. full status check can be done after all erase and write sequences complete. write ffh after the last operation to reset the device to read array mode. 0 0606_07 figure 7. write to buffer flowchart
e intel ? strataflash? memory technology, 32 and 64 mbit 35 preliminary start write 40h, address write data and address read status register sr.7 = full status check if desired byte/word program complete read status register data (see above) voltage range error device protect error programming error byte/word program successful sr.3 = sr.1 = sr.4 = full status check procedure bus operation write write standby repeat for subsequent programming operations. sr full status check can be done after each program operation, or after a sequence of programming operations. write ffh after the last program operation to place device in read array mode. bus operation standby standby sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are programmed before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. 0 1 1 0 1 0 1 0 command setup byte/ word program byte/word program comments data = 40h addr = location to be programmed data = data to be programmed addr = location to be programmed check sr.7 1 = wsm ready 0 = wsm busy command comments check sr.3 1 = programming to voltage error detect check sr.4 1 = programming error read status register data standby check sr.1 1 = device protect detect rp# = v ih , block lock-bit is set only required for systems implemeting lock-bit configuration. 0606_08 figure 8. byte/word program flowchart
intel ? strataflash? memory technology, 32 and 64 mbit e 36 preliminary erase block time-out? start read status register sr.7 = erase flash block(s) complete 0 1 no full status check if desired suspend erase no device supports queuing issue block queue erase command 28h, block address read extended status register is queue available? xsr.7= another block erase? issue erase command 28h block address read extended status register write confirm d0h block address another block erase? is queue full? xsr.7= 0=yes 1=no yes no 1=yes yes issue single block erase command 20h, block address no 0=no no suspend erase loop yes yes write confirm d0h block address set time-out issue read status command queued erase section (include this section for compatibility with future scs-compliant devices) bus operation command comments write erase block data = 28h or 20h addr = block address read xsr.7 = valid addr = x standby check xsr.7 1 = erase queue avail. 0 = no erase queue avail. write erase block data = 28h addr = block address read sr.7 = valid; sr.6 - 0 = x with the device enabled, oe# low updates sr addr = x standby check xsr.7 1 = erase queue avail. 0 = no erase queue avail. write (note 1) erase confirm data = d0h addr = x read status register data with the device enabled, oe# low updates sr addr = x standby check sr.7 1 = wsm ready 0 = wsm busy 1. the erase confirm byte must follow erase setup when the erase queue status (xsr.7) = 0. full status check can be done after all erase and write sequences complete. write ffh after the last operation to reset the device to read array mode. yes 0606_09 figure 9. block erase flowchart
e intel ? strataflash? memory technology, 32 and 64 mbit 37 preliminary start write b0h read status register sr.7 = sr.6 = block erase completed read or program? done? write d0h block erase resumed write ffh read array data program program loop read array data read no yes 1 1 0 0 bus operation command comments write erase suspend data = b0h addr = x read status register data addr = x standby check sr.7 1 - wsm ready 0 = wsm busy standby check sr.6 1 = block erase suspended 0 = block erase completed write erase resume data = d0h addr = x 0606_10 figure 10. block erase suspend/resume flowchart
intel ? strataflash? memory technology, 32 and 64 mbit e 38 preliminary start write 60h, block/device address write 01h/f1h, block/device address read status register sr.7 = full status check if desired set lock-bit complete full status check procedure bus operation write write standby repeat for subsequent lock-bit operations. full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations write ffh after the last lock-bit set operation to place device in read array mode. bus operation standby sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command, in cases where multiple lock-bits are set before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. 1 0 standby command set block/master lock-bit setup set block or master lock-bit confirm comments data = 60h addr =block address (block), device address (master) data = 01h (block) f1h (master) addr = block address (block), device address (master) check sr.7 1 = wsm ready 0 = wsm busy command comments check sr.3 1 = programming voltage error detect check sr.1 1 = device protect rp# = v ih (set master lock-bit operation) rp# = v ih , master lock-bit is set (set block lock-bit operation) read status register data (see above) voltage range error device protect error sr.3 = sr. 1 = 1 0 1 0 command sequence error sr.4,5 = 1 0 set lock-bit error sr.4 = 1 0 read status register data standby check sr.4, 5 both 1 = command sequence error standby check sr.4 1 = set lock-bit error set lock-bit successful 0606_11 figure 11. set block lock-bit flowchart
e intel ? strataflash? memory technology, 32 and 64 mbit 39 preliminary start write 60h write d0h read status register sr.7 = full status check if desired clear block lock-bits complete full status check procedure bus operation write write standby write ffh after the clear lock-bits operation to place device in read array mode. bus operation standby sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command. if an error is detected, clear the status register before attempting retry or other error recovery. 1 0 standby command clear block lock-bits setup clear block or lock-bits confirm comments data = 60h addr = x data = d0h addr = x check sr.7 1 = wsm ready 0 = wsm busy command comments check sr.3 1 = programming voltage error detect check sr.1 1 = device protect rp# = v ih , master lock-bit is set read status register data (see above) voltage range error device protect error sr.3 = sr. 1 = 1 0 1 0 command sequence error sr.4,5 = 1 0 clear block lock-bits error sr.5 = 1 0 read status register data standby check sr.4, 5 both 1 = command sequence error standby check sr.5 1 = clear block lock-bits error clear block lock-bits successful 0606_12 figure 12. clear block lock-bit flowchart
intel ? strataflash? memory technology, 32 and 64 mbit e 40 preliminary 5.0 design considerations 5.1 three-line output control the device will often be used in large memory arrays. intel provides five control inputs (ce 0 , ce 1 , ce 2 , oe#, and rp#) to accommodate multiple memory connections. this control provides for: a. lowest possible memory power dissipation. b. complete assurance that data bus contention will not occur. to use these control inputs efficiently, an address decoder should enable the device (see table 2, chip enable truth table ) while oe# should be connected to all memory devices and the systems read# control line. this assures that only selected memory devices have active outputs while de- selected memory devices are in standby mode. rp# should be connected to the system powergood signal to prevent unintended writes during system power transitions. powergood should also toggle during system reset. 5.2 sts and block erase, program, and lock-bit configuration polling sts is an open drain output that should be connected to v ccq by a pull-up resistor to provide a hardware method of detecting block erase, program, and lock-bit configuration completion. in default mode, it transitions low after block erase, program, or lock-bit configuration commands and returns to high z when the wsm has finished executing the internal algorithm. for alternate configurations of the sts pin, see the configuration command. sts can be connected to an interrupt input of the system cpu or controller. it is active at all times. sts, in default mode, is also high z when the device is in block erase suspend (with programming inactive) or in reset/power-down mode. 5.3 power supply decoupling flash memory power switching characteristics require careful device decoupling. system designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of ce 0 , ce 1 , ce 2 , and oe#. transient current magnitudes depend on the device outputs capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. since intel strataflash memory devices draw their power from three v cc pins (these devices do not include a v pp pin), it is recommended that systems wit hout separate power and ground planes attach a 0.1 f ceramic capacitor between each of the devices three v cc pins (this includes v ccq ) and ground. these high-frequency, low-inductance capacitors should be placed as close as possible to package leads on each strataflash device. each device should have a 0.1 f ceramic capacitor connected between its v cc and gnd. these high-frequency, low inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices, a 4.7 f electrolytic capacitor should be placed between v cc and gnd at the arrays power supply connection. the bulk capacitor will overcome voltage slumps caused by pc board trace inductance. 5.4 v cc , v pen , rp# transitions block erase, program, and lock-bit configuration are not guaranteed if v pen or v cc falls outside of the specified operating ranges, or rp# 1 v ih or v hh . if rp# transitions to v il during block erase, program, or lock-bit configuration, sts (in default mode) will remain low for a maximum time of t plph + t phrh until the reset operation is complete. then, the operation will abort and the device will enter reset/power-down mode. the aborted operation may leave data partially corrupted after programming, or partially altered after an erase or lock-bit configuration. therefore, block erase and lock-bit configuration commands must be repeated after normal operation is restored. device power-off or rp# = v il clears the status register.
e intel ? strataflash? memory technology, 32 and 64 mbit 41 preliminary the cui latches commands issued by system software and is not altered by v pen , ce 0 , ce 1 , or ce 2 transitions, or wsm actions. its state is read array mode upon power-up, after exit from reset/power-down mode, or after v cc transitions below v lko . v cc must be kept at or above v pen during v cc transitions. after block erase, program, or lock-bit configuration, even after v pen transitions down to v penlk , the cui must be placed in read array mode via the read array command if subsequent access to the memory array is desired. v pen must be kept at or below v cc during v pen transitions. 5.5 power-up/down protection the device is designed to offer protection against accidental block erasure, programming, or lock-bit configuration during power transitions. internal circuitry resets the cui to read array mode at power-up. a system desi gner must guard against spurious writes for v cc voltages above v lko when v pen is active. since we# must be low and the device enabled (see table 2, chip enable truth table ) for a command write, driving we# to v ih or disabling the device will inhibit writes. the cuis two-step command sequence architecture provides added protection against data alteration. keeping v pen below v penlk prevents inadvertent data alteration. in-system block lock and unlock capability protects the device against inadvertent programming. the device is disabled while rp# = v il regardless of its control inputs. 5.6 power dissipation when designing portable systems, desi gners must consider battery power consumption not only during device operation, but also for data retention during system idle time. flash memorys nonvolatility increases usable battery life because data is retained when system power is removed.
intel ? strataflash? memory technology, 32 and 64 mbit e 42 preliminary 6.0 electrical specifications 6.1 absolute maximum ratings* temperature under bias expanded .............................. C20 c to +70 c storage temperature................. C65 c to +125 c voltage on any pin (except rp#) ............................................ C2.0 v to +7.0 v (1) rp# voltage with respect to gnd during lock-bit configuration operationsC2.0 v to +14.0 v (1,2,3) output short circuit current.....................100 ma (4) notice: this datasheet contains preliminary information on new products in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design . *warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. notes: 1. all specified voltages are with respect to gnd. minimum dc voltage is C0.5 v on input/output pins and C0.2 v on v cc and v pen pins. during transitions, this level may undershoot to C2.0 v for periods <20 ns. maximum dc voltage on input/output pins, v cc , and v pen is v cc +0.5 v which, during transitions, may overshoot to v cc +2.0 v for periods <20 ns. 2. maximum dc voltage on rp# may overshoot to +14.0 v for periods <20 ns. 3. rp# voltage is normally at v il or v ih . connection to supply of v hh is allowed for a maximum cumulative period of 80 hours. 4. output shorted for no more than one second. no more than one output shorted at a time. 6.2 operating conditions temperature and v cc operating conditions symbol parameter notes min max unit test condition t a operating temperature C20 +70 c ambient temperature v cc v cc1 supply voltage (5 v 10%) 4.50 5.50 v v ccq1 v ccq1 supply voltage (5 v 10%) 4.50 5.50 v v ccq2 v ccq2 supply voltage (2. 7v - 3.6 v) 2.70 3.60 v 6.3 capacitance (1) t a = +25c, f = 1 mhz symbol parameter typ max unit condition c in input capacitance 6 8 pf v in = 0.0 v c out output capacitance 8 12 pf v out = 0.0 v note: 1. sampled, not 100% tested.
e intel ? strataflash? memory technology, 32 and 64 mbit 43 preliminary 6.4 dc characteristics sym parameter notes typ max unit test conditions i li input and v pen load current 1 1 m av cc = v cc max v in = v cc or gnd i lo output leakage current 1 10 m av cc = v cc max v in = v cc or gnd i ccs v cc standby current 1,3,5 80 150 m a cmos inputs, v cc = v cc max, ce 0 = ce 1 = ce 2 = rp# = v ccq1 0.2 v 450 900 m a cmos inputs, rp# = v cc = v cc max, ce 0 = ce 1 = ce 2 = v ccq2 min 325 650 m a cmos inputs, rp# = v cc = v cc max, ce 2 = gnd, ce 0 = ce 1 = v ccq2 min 210 400 m a cmos inputs, rp# = v cc = v cc max, ce 1 = ce 2 = gnd, ce 0 = v ccq2 min or ce 0 = ce 2 = gnd, ce 1 = v ccq2 min 0.71 2 ma ttl inputs, v cc = v cc max, ce 0 = ce 1 = ce 2 = rp# = v ih i ccd v cc power-down current 80 125 m a rp# = gnd 0.2v i out (sts) = 0 ma i ccr v cc read current 1,5,6 35 55 ma cmos inputs, v cc = v ccq =v cc max device is enabled (see table 2, chip enable truth table ) f = 5 mhz i out = 0 ma 45 65 ma ttl inputs ,v cc = v cc max device is enabled (see table 2, chip enable truth table ) f = 5 mhz i out = 0 ma i ccw v cc program or set 1,6,7 35 60 ma cmos inputs, v pen = v cc lock-bit current 40 70 ma ttl inputs, v pen = v cc i cce v cc block erase or clear block lock-bits 1,6,7 35 70 ma cmos inputs, v pen = v cc current 40 80 ma ttl inputs, v pen = v cc i cces v cc block erase suspend current 1,2 10 ma device is disabled (see table 2, chip enable truth table )
intel ? strataflash? memory technology, 32 and 64 mbit e 44 preliminary 6.4 dc characteristics (continued) sym parameter notes min max unit test conditions v il input low voltage 7 C0.5 0.8 v v ih input high voltage 7 2.0 v cc + 0.5 v v ol output low voltage 3,7 0.45 v v ccq = v ccq1 min i ol = 5.8 ma 0.4 vv ccq = v ccq2 min i ol = 2 ma v oh1 output high voltage (ttl) 3,7 2.4 v v ccq = v ccq1 min or v ccq = v ccq2 min i oh = C2.5 ma (v ccq1 ) C2 ma (v ccq2 ) v oh2 output high voltage (cmos) 3,7 0.85 v ccq v v ccq = v ccq1 min or v ccq = v ccq2 min i oh = C2.5 ma v ccq C0.4 v v ccq = v ccq1 min or v ccq = v ccq2 min i oh = C100 a v penlk v pen lockout during normal operations 4,7,11 3.6 v v penh v pen during block erase, program, or lock-bit operations 4,11 4.5 5.5 v v lko v cc lockout voltage 8 3.25 v v hh rp# unlock voltage 9,10 11.4 12.6 v set master lock-bit override lock-bit notes: 1. all currents are in rms unless otherwise noted. these currents are valid for all product versions (packages and speeds). contact intels application support hotline or your local sales office for information about typical specifications. 2. i cces is specified with the device de-selected. if the device is read or written while in erase suspend mode, the devices current draw is i ccr or i ccw . 3. includes sts. 4. block erases, programming, and lock-bit configurations are inhibited when v pen v penlk , and not guaranteed in the range between v penlk (max) and v penh (min), and above v penh (max). 5. cmos inputs are either v cc 0.2 v or gnd 0.2 v. ttl inputs are either v il or v ih . 6. add 5 ma for v ccq = v ccq2 min. 7. sampled, not 100% tested. 8. block erases, programming, and lock-bit configurations are inhibited when v cc < v lko , and not guaranteed in the range between v lko (min) and v cc (min), and above v cc (max). 9. master lock-bit set operations are inhibited when rp# = v ih . block lock-bit configuration operations are inhibited when the master lock-bit is set and rp# = v ih . block erases and programming are inhibited when the corresponding block-lock bit is set and rp# = v ih . block erase, program, and lock-bit configuration operations are not guaranteed and should not be attempted with v ih < rp# < v hh . 10. rp# connection to a v hh supply is allowed for a maximum cumulative period of 80 hours. 11. tie v pen to v cc (4.5 vC5.5 v).
e intel ? strataflash? memory technology, 32 and 64 mbit 45 preliminary output test points input 2.0 0.8 2.0 0.8 2.4 0.45 ac test inputs are driven at v oh (2.4 v ttl ) for a logic "1" and v ol (0.45 v ttl ) for a logic "0." input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ). output timing ends at v ih and v il . input rise and fall times (10% to 90%) <10 ns. figure 13. transient input/output reference waveform for v ccq = 5.0 v 10% (standard testing configuration) output test points input 1.35 2.7 0.0 1.35 ac test inputs are driven at 2.7v for a logic "1" and 0.0v for a logic "0." input timing begins, and output timing ends, at 1.3 5 v (50% of v ccq ). input rise and fall times (10% to 90%) <10 ns. figure 14. transient input/output reference waveform for v ccq = 2.7 v - 3.6 v device under test out r l = 3.3 k w 1n914 1.3v c l note: c l includes jig capacitance figure 15. transient equivalent testing load circuit test configuration capacitance loading value test configuration c l (pf) v ccq = 5.0 v 10% 100 v ccq = 2.7 v - 3.6 v 50
intel ? strataflash? memory technology, 32 and 64 mbit e 46 preliminary 6.5 ac characteristics read-only operations (1) versions 5 v 10% v ccq C100/C150 (4) C120 (4) (all units in ns unless otherwise noted) 2.7 v3.6v v ccq C100/C150 (4) C120 (4) # sym parameter notes min max min max r1 t avav read/write cycle time 32 mbit 100 120 64 mbit 150 r2 t avqv address to output delay 32 mbit 100 120 64 mbit 150 r3 t elqv ce x to output delay 32 mbit 2 100 120 64 mbit 2 150 r4 t glqv oe# to output delay 2 50 50 r5 t phqv rp# high to output delay 32 mbit 180 180 64 mbit 210 r6 t elqx ce x to output in low z 3 0 0 r7 t glqx oe# to output in low z 3 0 0 r8 t ehqz ce x high to output in high z 3 55 55 r9 t ghqz oe# high to output in high z 3 15 15 r10 t oh output hold from address, ce x , or oe# change, whichever occurs first 30 0 r11 t elfl t elfh ce x low to byte# high or low 3 10 10 r12 t flqv t fhqv byte# to output delay 1000 1000 r13 t flqz byte# to output in high z 3 1000 1000 r14 t ehel cex pulse width 3 10 10 notes: ce x low is defined as the first edge of ce 0 , ce 1 , or ce 2 that enables the device. ce x high is defined at the first edge of ce 0 , ce 1 , or ce 2 that disables the device (see table 2, chip enable truth table ). 1. see figure 16, ac waveform for read operations for the maximum allowable input slew rate. 2. oe# may be delayed up to t elqv -t glqv after the first edge of ce 0 , ce 1 , or ce 2 that enables the device (see table 2, chip enable truth table ) without impact on t elqv . 3. sampled, not 100% tested. 4. see figures 13 C15, transient input/output reference waveform for v ccq = 5.0 v 10%, transient input/output reference waveform for v ccq = 2.7 v C3.6 v, and transient equivalent testing load circuit for testing characteristics.
e intel ? strataflash? memory technology, 32 and 64 mbit 47 preliminary r1 r14 r8 r10 high z r13 r11 r12 r6 r5 r4 r3 r7 r2 r9 valid output address stable data valid device address selection standby addresses [a] v ih v il v ih v il disabled (v ih ) enabled (v il ) ce x [e] v ih v il v oh v ol v ih v il v ih v il v ih v il oe# [g] we# [w] data [d/q] dq 0 -dq 15 v cc rp# [p] byte# [f] high z 0606_16 notes: ce x low is defined as the first edge of ce 0 , ce 1 , or ce 2 that enables the device. ce x high is defined at the first edge of ce 0 , ce 1 , or ce 2 that disables the device (see table 2, chip enable truth table ). figure 16. ac waveform for read operations
intel ? strataflash? memory technology, 32 and 64 mbit e 48 preliminary 6.6 ac characteristics write operations (1,2) versions valid for all speeds # sym parameter notes min max unit w1 t phwl ( t phel ) rp# high recovery to we# (ce x ) going low 31 s w2 t elwl (t wlel )ce x (we#) low to we# (ce x ) going low 8 0 ns w3 t wp write pulse width 8 70 ns w4 t dvwh ( t dveh ) data setup to we# (ce x ) going high 4 50 ns w5 t avwh ( t aveh ) address setup to we# (ce x ) going high 4 50 ns w6 t wheh ( t ehwh ) ce x (we#) hold from we# (ce x ) high 10 ns w7 t whdx ( t ehdx ) data hold from we# (ce x ) high 0 ns w8 t whax ( t ehax ) address hold from we# (ce x ) high 0 ns w9 t wph write pulse width high 9 30 ns w10 t phhwh ( t phheh ) rp# v hh setup to we# (ce x ) going high 3 0 ns w11 t vpwh ( t vpeh ) v pen setup to we# (ce x ) going high 3 0 ns w12 t whgl ( t ehgl ) write recovery before read 6 35 ns w13 t whrl ( t ehrl ) we# (ce x ) high to sts going low 5 90 ns w14 t qvph rp# v hh hold from valid srd, sts going high 3,5,7 0 ns w15 t qvvl v pen hold from valid srd, sts going high 3,5,7 0 ns notes: ce x low is defined as the first edge of ce 0 , ce 1 , or ce 2 that enables the device. ce x high is defined at the first edge of ce 0 , ce 1 , or ce 2 that disables the device (see table 2, chip enable truth table ). 1. read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. refer to ac characteristics Cread-only operations . 2. a write operation can be initiated and terminated with either ce x or we#. 3. sampled, not 100% tested. 4. refer to table 4 for valid a in and d in for block erase, program, or lock-bit configuration. 5. sts timings are based on sts configured in its ry/by# default mode. 6. for array access, t avqv is required in addition to t whgl for any accesses after a write. 7. v pen should be held at v penh (and if necessary rp# should be held at v hh ) until determination of block erase, program, or lock-bit configuration success (sr.1/3/4/5 = 0). 8. write pulse width (t wp ) is defined from ce x or we# going low (whichever goes low first) to ce x or we# going high (whichever goes high first). hence, t wp = t wlwh = t eleh = t wleh = t elwh . if ce x is driven low 10 ns before we# going low, we# pulse width requirement decreases to t wp - 10 ns. 9. write pulse width high (t wph ) is defined from ce x or we# going high (whichever goes high first) to ce x or we# going low (whichever goes low first). hence, t wph = t whwl = t ehel = t whel = t ehwl .
e intel ? strataflash? memory technology, 32 and 64 mbit 49 preliminary a in a in ab c d e f w15 d in w11 w10 valid srd d in d in w13 w14 w7 w3 w4 high z w2 w9 w16 w12 w6 w1 w5 w8 v ih v il addresses [a] disabled (v ih ) enabled (v il ) ce x , (we#) [e(w)] v ih v il oe# [g] disabled (v ih ) enabled (v il ) we#, (ce x ) [w(e)] v ih v il data [d/q] v oh v ol sts [r] v ih v il rp# [p] v hh v penlk v il v pen [v] v penh 0606_17 notes: ce x low is defined as the first edge of ce 0 , ce 1 , or ce 2 that enables the device. ce x high is defined at the first edge of ce 0 , ce 1 , or ce 2 that disables the device (see table 2, chip enable truth table ). sts is shown in its default mode (ry/by#). 1. v cc power-up and standby. 2. write block erase, write buffer, or program setup. 3. write block erase or write buffer confirm, or valid address and data. 4. automated erase delay. 5. read status register or query data. 6. write read array command. figure 17. ac waveform for write operations
intel ? strataflash? memory technology, 32 and 64 mbit e 50 preliminary sts (r) rp# (p) v ih v il v ih v il p1 p2 0606_18 notes: sts is shown in its default mode (ry/by#). figure 18. ac waveform for reset operation reset specifications (1) # sym. parameter notes min max unit p1 t plph rp# pulse low time (if rp# is tied to v cc , this specification is not applicable) 235 s p2 t phrh rp# high to reset during block erase, program, or lock-bit configuration 3 100 ns notes: 1. these specifications are valid for all product versions (packages and speeds). 2. if rp# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the minimum required rp# pulse low time is 100 ns. 3. a reset time, t phqv , is required from the latter of sts (in ry/by# mode) or rp# going high until outputs are valid.
e intel ? strataflash? memory technology, 32 and 64 mbit 51 preliminary 6.7 block erase, program, and lock-bit configuration performance (3,4) # sym parameter notes min typ (1) max unit w16 t whqv1 t ehqv1 write buffer byte program time 2,5 tbd 6.3 tbd s w16 t whqv2 t ehqv2 write buffer word program time 2,5 tbd 12.6 tbd s w16 t whqv3 t ehqv3 byte program time (using word/byte program command) 2 tbd 180 tbd s block program time (using write to buffer command) 2 tbd 0.8 tbd sec w16 t whqv4 t ehqv4 block erase time 2 tbd 0.7 tbd sec w16 t whqv5 t ehqv5 set lock-bit time 2 tbd 32 tbd s w16 t whqv6 t ehqv6 clear block lock-bits time 2 tbd 0.3 tbd sec w16 t whrh t ehrh erase suspend latency time to read 26 tbd s notes: 1. typical values measured at t a = +25 c and nominal voltages. assumes corresponding lock-bits are not set. subject to change based on device characterization. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. sampled but not 100% tested. 5. these values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary.
intel ? strataflash? memory technology, 32 and 64 mbit e 52 preliminary 7.0 ordering information g 2 8 f 6 4 0 j 5 - 1 5 0 package g = 56-ball bga* csp e = 56-lead tsop da = 56-lead ssop product line designator for all intel ? flash products access speed (ns) (100, 120, 150) product family j = intel ? strataflash tm memory, 2 bits-per-cell device density 640 = x8/x16 (64 mbit) 320 = x8/x16 (32 mbit) voltage (v cc /v pen ) 5 = 5 v/5 v valid operational conditions order code by density 5 v v cc 32 mbit 64 mbit 2.7 v C 3.6 v v ccq 5 v 10% v ccq da28f320j5-100 da28f320j5-120 da28f640j5-150 yes yes E28F320J5-100 e28f320j5-120 yes yes g28f640j5-150 yes yes
e intel ? strataflash? memory technology, 32 and 64 mbit 53 preliminary 8.0 additional information (1,2) order number document 210830 flash memory databook 292123 ap-374 flash memory write protection techniques 292203 ap-644 intel ? strataflash? memory migration guide 292204 ap-646 common flash interface (cfi) and command sets 292205 ap-647 intel ? strataflash? memory design guide 297848 intel ? strataflash? memory 32 and 64 mbit specification update note: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools.

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